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RAMs can be classified into two types: "static" and "dynamic."
In a static RAM, each bit is represented by the state of a circuit
with two stable states. Such a "bistable" circuit can be built with four
transistors (for maximum density) or six (for highest speed and lowest
power). Static RAMs (SRAMs) are available in many configurations.
(Almost) all SRAMs have one pin per address line, and all of them
are able to store data for as long as power is applied, without any
external circuit activity.
In a dynamic RAM (DRAM), each bit is represented by the charge on a
*very* small (30-50 femptofarads) capacitor, which is built into a
single, specialized transistor. DRAM storage cells take only about
a quarter of the silicon area that SRAM cells take, and silicon
area translates into cost.
The cells in a DRAM are organized into rows and columns. To access
a bit, you first select its row, and then you select its column.
Unfortunately, the charge leaks off the capacitor over time,
so each cell must be periodically "refreshed" by reading it and
writing it back. This happens automatically whenever a row is accessed.
After you're finished accessing a row, you have to give the DRAM time
to copy the row of bits back to the cells: the "precharge" time.
Because the row and column addresses are not needed at the same
time, they share the same pins. This makes the DRAM package smaller
and cheaper, but it makes the problem of distributing the signals
in the memory array difficult, because the timing becomes so
critical. Signal integrity in the memory array is one of the
things that differentiate a lousy motherboard from a high quality
one.